| Submission Open for Jan-Dec-2024 |
| Last Date of Submission : |
| 20th, April-2024 |
| Acceptance Notification : |
After Peer Review |
| Last Date of Publication : |
| 30th, April-2024 |
Volume10 ISSUE 1 Call for Conference Special Issue Archive (Recent Update ISSUE)
| S.NO | TITLE | PAGE NO | DOWNLOAD | |
| IJVDCS 30 | VLSI Realization of An Area Optimized EDDR Architecture Authors:CHUNDURI I V RAMANA, GONDU ANANTHA RAO |
0156-0159 |
Download | |
| IJVDCS 31 | Design of Approximate VLSI Architectures for Filter Design Optimization Authors:JILLALA VENKATESH, K. HARI, VENTRAPRAGADA TEJU |
0160-0168 |
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| IJVDCS 32 | Combining Efficiency, Fidelity, and Flexibility for Collaborative Cloud and Grid Computing Authors:S. SHASHA VALI, NUSRATH KHAN, DR. S. SENTHIL KUMAR, DR. S. SREENATHA REDDY, DR. M. NARENDRA KUMAR |
0169-0177 |
Download | |
| IJVDCS 33 | Online Testing for Three Fault Models in Reversible Circuits Authors:D. SOWMYA, D. CHANDRA PRAKASH |
0178-0185 |
Download | |
| IJVDCS 34 | Fully Reused VLSI Architecture of FM0/Manchester Encoding using SOLS Technique for DSRC Applications Authors:GEGHANNA ARUN KUMAR, PATHAN MOHD BASHA KHAN |
0186-0191 |
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| IJVDCS 35 | Low-Power Programmable PRPG with Test Compression Capabilities Authors:KARISHMA, PATHAN MOHD BASHA KHAN |
0192-0199 |
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| IJVDCS 36 | An FPGA Implementation of Design Considerations for Ultra-Low Energy Adder Architecture Authors:M. CHITTI BABU, VENTRAPRAGADA TEJU |
0200-0206 |
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| IJVDCS 37 | Performance Analysis of Pulsed Latches Based Shift Register Using Power Reduction Techniques Authors:KADIYALA VENKATA LAKSHMI, M. SUNIL BABU |
0207-0210 |
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| IJVDCS 38 | Implementation of Testable Reversible Sequential Circuit on FPGA Authors:GETTY MEENA, J. LINGAIAH, K. SRIDEVI |
0211-0216 |
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| IJVDCS 39 | A Novel Realization of Reversible LFSR for Its Application in Cryptography Authors:MURARKAR SRIKANTH, PATHAN MOHD BASHA KHAN |
0217-0220 |
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